Verification Engineer

Verification Engineer Overview

Fractile is at the forefront of developing silicon, systems, and software to overcome the memory wall, a critical hardware limitation affecting the advancement of artificial intelligence. As a Verification Engineer, you will play a vital role in enhancing the performance of AI technologies by ensuring the quality of integrated circuit products designed for data centers.

This position is ideal for individuals with a passion for verification who are eager to push the boundaries of the field. You will collaborate with a diverse team, contributing to discussions on specifications and architecture while ensuring that our RTL releases meet the highest standards of quality.

Key Responsibilities:

• Engage actively in the development of world-class machine learning and AI integrated circuit products aimed at data center applications.
• Contribute to the verification process by ensuring that RTL releases meet the highest functional quality standards.
• Participate in discussions regarding specifications and architecture, as well as the workflows that connect these elements.
• Collaborate closely with teams involved in modeling, system architecture, and RTL design to enhance product quality.
• Drive improvements in established practices to enhance tape-out quality and reduce costs.

Required Skills and Experience:

• A minimum of 3 years of experience in a relevant field.
• Strong software programming skills, particularly in Python or another object-oriented language such as C++.
• Understanding of digital hardware concepts and the ability to read and debug RTL in SystemVerilog.
• Familiarity with debugging waveforms and a strong software background, with candidates encouraged to apply even without extensive RTL experience.

Desirable Skills and Experience:

• Experience in pre-silicon RTL verification and verification planning from specification.
• Ability to build testbenches, create stimulus, and perform functional modeling of hardware blocks.
• Familiarity with SystemVerilog Assertions (SVA) and open-source tools for silicon development.
• Experience working in a monorepo environment and contributing to architecture discussions.

Benefits:

• Competitive salaries and meaningful equity options.
• Standard company benefits.
• A culture that values diverse perspectives and encourages applications from underrepresented groups in engineering.
• Hybrid working model requiring 2-3 days in the London or Bristol offices.

Fractile is committed to transparency regarding compliance with UK and international export control regulations, and certain roles may require additional eligibility checks. We are excited to welcome innovative minds to our team as we tackle the challenges of the future.

Degree Requirement: Not Specified

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